1. Field of the Invention
This disclosure generally relates to structures and methods of making an offset-trench crackstop that forms an air gap in an opening of a passivation layer which overlies and is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die.
2. Description of Related Art
In manufacturing semiconductor devices, a number of integrated circuits (ICs) are simultaneously prepared on a semiconductor wafer by conventional photolithography techniques. The ICs, which are rectangular in shape, are disposed in a grid pattern on the semiconductor wafer. Each of the four sides of each individual IC is adjacent to a dicing channel. The individual ICs are singulated by dicing the wafer along the dicing channels with either a saw or laser to form IC dies or chips.
Referring to FIG. 1, an individual IC die or chip 100 includes an active device region 150 that comprises active and passive electrical devices, which provide the IC's functionality, and a peripheral boundary region 110 that is adjacent to the dicing lanes (not shown) in a wafer. The active and passive electrical devices are formed within the semiconductor layers of the active device region 150, which is located behind a metal crackstop 130 that separates the active device region 150 from the peripheral boundary region 110. The IC die 100, including both the active device region 150 and the peripheral boundary region 110, is covered by a plurality of metallization layers. Each of the metallization layers includes a patterned intermetallic dielectric layer that includes vias or via bars and a patterned metal layer, usually comprising aluminum (Al). Within the active device region 150, each of the patterned metal layers includes electrical interconnections to the active and passive electrical devices of the IC die 100 that are contacted by the vias.
Upon dicing, the IC die or chip is subject to crack ingress forces along its sides and at the corners. Conventionally, a metal crackstop is formed parallel to the rectangular perimeter of the IC die to prevent the crack ingress forces from delaminating or cracking the electrical devices and the metallization layers of the active device region. Referring to FIG. 2, a cross section of a four layer 201-204 metal crackstop, along the axes of its sides, includes a plurality of alternating patterned metal layers 230 and metal via bars 220 formed on the silicon layer 215 of the perimeter boundary region, each layer being formed by processes identical to those used in forming the patterned metal layers and vias of the metallization layers in the active device region of the IC die. A passivation layer 255 is formed on the topmost metallization layer that covers the top metal layer 230 of the metal crackstop. Typically, the passivation layer 255 comprises any of a silicon nitride (SiN) layer and a silicon oxide (SiO2) layer.
Referring to FIG. 3, a cross section of a dicing channel region, crackstop region and active device region of an IC die 300 illustrates a conventional crackstop 370, which forms an air gap, and a via hole 375 that are formed in a passivation layer 355 of an IC die 300. As is known in the art, the conventional crackstop 370, which forms an air gap that overlies the metal via bars and patterned metal layers of the metal crackstop in the crackstop region, prevents inward propagation of cracks from the adjacent dicing channel through the passivation layer 335 into the active device region of the IC die 300; whereas formation of via hole 375 in the passivation layer 335 facilitates the subsequent formation of bonding pads 360 and electrical connectors used in flip chip packaging.
Recently, a copper (Cu) pillar process has been introduced into the processes of flip chip packaging. In the Cu pillar process, a Cu seed layer is deposited on exposed portions of a top metal layer 330 of the IC die 300 through via hole 375 to form bonding pads 360 for a Cu pillar or bump. However, when a conventional crackstop 370, which forms an air gap over the top metal layer 330 of the metal crackstop in the passivation layer 335, Cu is also deposited on the top metal layer 330 of the metal crackstop in the Cu pillar process. A wet etch used to remove the Cu from the top metal layer 330 of the metal crackstop is problematic, because it also attacks aluminum (Al) in the top metal layer 330, resulting in visual defects that prevent inspection of the packaging process.
In an additional flip chip packaging process, the physical layout of electrically conductive redistribution layers overlying the IC die would be less constrained, if the redistribution layers were placed over the metal crackstop. Such less constrained layouts, however, cannot be implemented because the redistribution layers would short-out to the underlying metal crackstop.
There remains a need to prevent inward propagation of cracks by an improved crackstop that forms an air gap in a passivation layer on a crackstop region of an integrated circuit (IC) die, while allowing copper (Cu) deposition through a via hole on exposed portions of a top metal layer in an active device region of the IC die.